EECS 472 · MDE

Sorry, our processor
is out of order

Designing an out-of-order RISC-V core

Marco Boone
with Niki Lin, Shaoqian Zhou, and Sophia Chen

TC 496 · University of Michigan · October 2026

EECS 472: learn computer architecture by building a CPU

Class

EECS 472 is my MDE: a semester-long project for teams of 4-5

Purpose

Learn how fast processors work by designing, verifying, and synthesizing one in SystemVerilog

Project

A 2-wide superscalar, out-of-order RISC-V core in the style of the MIPS R10K that can run C programs

The problem: one cache miss stalls the pipeline

Timeline of five instructions. In order, a cache-missing load stalls the four instructions behind it and the sequence takes 9 cycles. Out of order, three independent instructions run during the miss and the sequence takes 6 cycles.

The solution: execute out of order, commit in order

Five stages: fetch and decode, dispatch, issue, execute, commit. Under each stage, four instructions: lw, add, mul, sub, where the first add needs the result of lw. Fetch and dispatch keep program order. At issue, the dependent add waits for lw while mul and sub go ahead. At execute, mul and sub run during the load miss, then lw, then the dependent add. Commit restores program order: lw, add, mul, sub.

Our core: front, middle, and back end

High-level block diagram of the HEADTH(e)ROB processor: front end with instruction cache, branch predictors, and decoder; middle end with reorder buffer, reservation station, and load-store unit; back end with functional units; connected by a common data bus.

Our method: interface, build, integrate, test, repeat

Four-step loop: interface (agree on module signals), build (modules in pairs), integrate (into the full core), test (run programs against reference output), then repeat for each new feature. Risk management: correctness first, then speed. The group meets about twice a week.

Our goals: core by Oct 29, full CPU by Nov 20

Timeline from September 22 to December 11. Completed: design review October 7, middle end structures integrated October 10, and branch recovery October 20. Today, October 22: backend and ETB. Upcoming: milestone October 29, design freeze November 20, final report December 11.

In summary

EECS 472 a semester-long team project to build a CPU

The problem one slow load stalls everything behind it

The solution run ready instructions early, commit in program order

Our core a 2-wide, R10K-style front, middle, and back end

Our method small tested pieces, integrated and repeated per feature

Our goals working core by Oct 29, full CPU by Nov 20

References

[1] K. C. Yeager, “The MIPS R10000 superscalar microprocessor,” IEEE Micro, vol. 16, no. 2, pp. 28–41, Apr. 1996.

[2] M. Boone, N. Lin, S. Zhou, and S. Chen, “Preliminary design review: an out-of-order RISC-V processor,” EECS 472, Univ. of Michigan, Oct. 2026.

[3] EECS 472 Final Project Specification, Univ. of Michigan, Fall 2026.